TDA8433, Elektronika, elementy
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INTEGRATED CIRCUITS
DATA SHEET
TDA8433
Deflection processor for computer
controlled TV receivers
Product specification
File under Integrated Circuits, IC02
August 1991
Philips Semiconductors
Product specification
Deflection processor for computer
controlled TV receivers
TDA8433
FEATURES
GENERAL DESCRIPTION
The TDA8433 is an I
2
C-bus
controlled deflection processor which,
together with a sync processor (e.g.
TDA2579A, see Fig.6), contains the
control and drive functions of the
deflection part in a computer
controlled TV receiver. The TDA8433
replaces all picture geometry settings
which were previously set manually
during manufacture.
·
I
2
C-bus interface
·
Input for vertical sync
·
Sawtooth generator with amplitude
independent of frequency
·
Vertical deflection output stage
driver
·
East-west raster correction drive
output
·
EHT modulation input
·
Changes picture width and height
without affecting geometry.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
V
CC
supply voltage (pin 12)
10.8
12.0
13.2
V
I
CC
supply current (pin 12)
12
20
27
mA
V
2
vertical sync trigger level
-
3
-
V
V
21
vertical feedback (note 1)
DC level
-
1.7
1.85
2.05
V
AC level
1.65
1.8
1.95
V
P
V
24
EHT compensation operating range
1.7
-
6
V
V
11-13
inputs for control register data:
not locked to video
-
0.7
1
V
at 50 Hz status
0.8 V
CC
-
-
V
at 60 Hz status
-
-
0.7 V
CC
V
V
10-13
HCENT comparator switching level
-
V
17
-
V
V
14-13
SDA I
2
C-bus switching level data input
-
3.5
-
V
V
15
SCL I
2
C-bus switching level clock input
-
3.5
-
V
V
1
device selection where:
Ao = '1'
9.0
-
V
CC
V
Ao = '0'
0
-
2.0
V
Note to quick reference data
1. VR
in
= 0; V-S-corr = 0; V
shift
= 20 H; V
ampl
= 20 H.
ORDERING INFORMATION
PACKAGE
EXTENDED TYPE NUMBER
PINS
PIN POSITION
MATERIAL
CODE
TDA8433
24
DIL
plastic
SOT101
(1)
Note
1. SOT101-1; 1996 December 2.
August 1991
2
Philips Semiconductors
Product specification
Deflection processor for computer
controlled TV receivers
TDA8433
Fig.1 Block diagram.
August 1991
3
Philips Semiconductors
Product specification
Deflection processor for computer
controlled TV receivers
TDA8433
PINNING
PIN
DESCRIPTION
1
Ao subaddress
2
vertical sync input
3
vertical blanking output
4
I
ref
resistor
5
vertical blanking/flyback timing capacitor
6
DACC (tau switching)
7
DACB (horizontal phase)
8
DACA (horizontal frequency)
9
OUT (video switch)
10
I/O (f
o
adjustment)
11
IN (HLOCKN
-
50/60 Hz)
12
positive supply +12 V
13
ground 1
14
serial data input
15
serial clock input
16
internal supply voltage
17
voltage reference for I/O
18
ground 2 (waveform)
19
east-west drive output
20
vertical drive output
21
vertical feedback
22
vertical sawtooth capacitor
23
vertical amplitude capacitor
Fig.2 Pinning diagram.
24
EHT input
August 1991
4
Philips Semiconductors
Product specification
Deflection processor for computer
controlled TV receivers
TDA8433
PIN FUNCTIONS
Pin 1 - Ao subaddress
Table 1 Sync processor time constants
The Ao bit is the least significant bit
of the bus-address. It enables two
TDA8433s, with different
addresses, to be connected to the
same bus.
VTRA
VTRC OUTPUT
TIME CONSTANT
'0'
'0'
12 V
automatic operation
'0'
'1'
5.3 V
medium
'1'
'0'
1.5 V
fast (video recorder)
'1'
'1'
0.2 V
not to be used
Pin 2 - Vertical sync input
3 V are
sufficient to exceed the internal
threshold of the ramp generator.
Flyback and blanking will then start
and, during the blanking period, the
circuit will be inhibited for further
input pulses (see Fig.3). It should be
noted that the TDA8433 has no
vertical oscillator therefore, the sync
processor, which is used in this
combination, has to provide trigger
pulses as well when the video input
is absent.
>
Pin 6 - DACC (tau switching)
The output voltage, which depends
on the VTRA and VTRC bits in the
I
2
C-bus control register, is connected
to the coincidence detector of the
sync processor. In this way the time
constants of the horizontal PLL (in the
sync processor) can be set. If the
TDA2579 is used (see Fig.6) the
effect will be as listed in Table 1.
CVBS = logic 1; the output is LOW
(saturation voltage)
An external video selector can be
controlled by means of this switching
function.
Pins 10 and 17 - I/O and Voltage
reference
Pin 10 is connected to the output of
the phase 1 detector in the sync
processor. Whether the pin is used as
an input or an output is dependent on
the PHI1 bit of the horizontal
frequency (HFREQ) register. When
PHI = logic 0 (output transistor open)
pin 10 is used as an input. The DC
information at this pin is compared
with the reference voltage at pin 17
and is reflected in the HCENT of the
status register.
Pin 7 - DACB (horizontal phase)
Pin 3 - Vertical blanking
The voltage at pin 7 is fed to the
horizontal pulse modulator in the sync
processor. This voltage, together with
the signal produced by the phase 2
detector during horizontal flyback,
sets the phase of the horizontal
output with respect to the flyback
pulse in the horizontal output stage.
The voltage range is variable
between 0.05 V and 10 V.
The positive going blanking pulse is
fed from a current source. The
blanking period is fixed by the
capacitor connected to pin 5 and the
resistor connected to pin 4 (see
Fig.3).
Pins 4 and 5 - Reference/flyback
timing
V
ref
at V
17
HCENT = logic 1; input
<
V
ref
at V
17
In this way the free running frequency
can be adjusted by computer while
the oscillator is locked. Alternatively,
when PHI1 = logic 1, pin 10 is
switched to ground. The free running
frequency of the oscillator can the be
adjusted while watching the screen
provided that pin 10 is connected to
the video input of the sync processor.
Pin 11 -IN (HLOCKN and 50/60 Hz)
>
The external resistor connected
between pin 4 and ground provides
a reference current for the triangle
generator circuit. This circuit
generates the triangle waveform at
pin 5. The width of the blanking
pulse is set by the external
capacitor connected to pin 5.
Pin 8 - DACA (horizontal
frequency)
The frequency of the horizontal
oscillator in the external sync
processor is adjusted by the voltage
level at pin 8. The voltage is variable
in 63 steps from 0.05 V to 10 V (i.e.
0.158 V per step).
Pin 9 - OUT (video switch)
The output at pin 9 is controlled by the
CVBS bit from the control register
where
CVBS = logic 0; the output is HIGH
(open collector)
This pin is connected to the combined
MUTE and 50/60 Hz pin of the sync
processor. The various DC levels
define the state of the HLOCKN and
50/60 Hz bits in the status register
(see Table 2.)
August 1991
5
Positive trigger pulses of
HCENT = logic 0; input
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